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lmz12002 snvs650h ? january 2010 ? revised august 2015 lmz12002 2-a simple switcher ? power module with 20-v maximum input voltage 1 features 2 applications 1 ? integrated shielded inductor ? point-of-load conversions from 5-v and 12-v input rail ? simple pcb layout ? time-critical projects ? flexible start-up sequencing using external soft- start capacitor and precision enable ? space-constrained high thermal requirement applications ? protection against inrush currents and faults such as input uvlo and output short circuit ? negative output voltage applications (see an-2027 snva425 ) ? junction temperature range ? 40 c to 125 c ? single exposed pad and standard pinout for easy 3 description mounting and manufacturing the lmz12002 simple switcher ? power module ? fast transient response for fpgas and asics is an easy-to-use step-down dc-dc solution capable ? low output voltage ripple of driving up to 2-a load with exceptional power conversion efficiency, line and load regulation, and ? pin-to-pin compatible with family devices: output accuracy. the lmz12002 is available in an ? lmz14203/2/1 (42-v maximum 3 a, 2 a, 1 a) innovative package that enhances thermal ? lmz12003/2/1 (20-v maximum 3 a, 2 a, 1 a) performance and allows for hand or machine ? fully webench ? power designer enabled soldering. ? performance benefits the lmz12002 can accept an input voltage rail between 4.5 v and 20 v, and can deliver an ? 12-w maximum total power output adjustable and highly accurate output voltage as low ? up to 2-a output current as 0.8 v. the lmz12002 only requires three external ? input voltage range 4.5 v to 20 v resistors and four external capacitors to complete the ? output voltage range 0.8 v to 6 v power solution. the lmz12002 is a reliable and robust design with the following protection features: ? efficiency up to 92% thermal shutdown, input undervoltage lockout, output ? electrical specifications overvoltage protection, short circuit protection, output ? operates at high ambient temperature with current limit, and the device allows start-up into a no thermal derating prebiased output. a single resistor adjusts the switching frequency up to 1 mhz. ? high efficiency reduces system heat generation device information (1) (2) ? low radiated emissions (emi) tested to part number package body size (nom) en55022 class b standard lmz12002 ndw (7) 9.85 mm 10.16 mm ? low external component count (1) for all available packages, see the orderable addendum at the end of the data sheet. (2) peak reflow temperature equals 245 c. see snaa214 for more details. simplified application schematic efficiency 5-v input at 25 c 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 output current (a) 25c 1.8 1.2 1.5 v in c in 10 p f enable r on see table r fbt c ff 0.022 p f see table c ss 0.022 p f r fbb see table 100 p f lmz12002 vout fb ron ss vin en gnd v out @ 2a productfolder sample &buy technical documents tools & software support &community
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com table of contents 1 features .................................................................. 1 8 application and implementation ........................ 14 8.1 application information ............................................ 14 2 applications ........................................................... 1 8.2 typical application ................................................. 14 3 description ............................................................. 1 9 power supply recommendations ...................... 20 4 revision history ..................................................... 2 10 layout ................................................................... 20 5 pin configuration and functions ......................... 3 10.1 layout guidelines ................................................. 20 6 specifications ......................................................... 3 10.2 layout examples ................................................... 21 6.1 absolute maximum ratings ...................................... 3 10.3 power dissipation and thermal considerations ... 22 6.2 esd ratings .............................................................. 3 10.4 power module smt guidelines ............................ 23 6.3 recommended operating conditions ....................... 4 11 device and documentation support ................. 24 6.4 thermal information .................................................. 4 11.1 device support ...................................................... 24 6.5 electrical characteristics ........................................... 4 11.2 documentation support ........................................ 24 6.6 typical characteristics ............................................. 6 11.3 community resources .......................................... 24 7 detailed description ............................................ 12 11.4 trademarks ........................................................... 24 7.1 overview ................................................................. 12 11.5 electrostatic discharge caution ............................ 24 7.2 functional block diagram ....................................... 12 11.6 glossary ................................................................ 24 7.3 feature description ................................................. 12 12 mechanical, packaging, and orderable 7.4 device functional modes ........................................ 13 information ........................................................... 25 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision g (october 2013) to revision h page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section. ................................................................................................. 1 changes from revision f (march 2013) to revision g page ? deleted 12 mils ....................................................................................................................................................................... 4 ? changed 10 mils ................................................................................................................................................................... 20 ? changed 10 mils ................................................................................................................................................................... 23 ? added power module smt guidelines ................................................................................................................................. 23 2 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 5 pin configuration and functions ndw package 7-pin top view pin functions pin type description name no. enable ? input to the precision enable comparator. rising threshold is 1.18-v nominal; 90- en 3 analog mv hysteresis nominal. maximum recommended input level is 6.5 v. exposed pad ? internally connected to pin 4. used to dissipate heat from the package ep ? ground during operation. must be electrically connected to pin 4 external to the package. feedback ? internally connected to the regulation, overvoltage, and short circuit fb 6 analog comparators. the regulation reference point is 0.8 v at this input pin. connected the feedback resistor divider between the output and ground to set the output voltage. gnd 4 ground ground ? reference point for all stated voltages. must be externally connected to ep. on-time resistor ? an external resistor from v in to this pin sets the on-time of the ron 2 analog application. typical values range from 25 k to 124 k . soft-start ? an internal 8- a current source charges an external capacitor to produce the ss 5 analog soft-start function. this node is discharged at 200 a during disable, overcurrent, thermal shutdown and internal uvlo conditions. supply input ? nominal operating range is 4.5 v to 20 v. a small amount of internal vin 1 power capacitance is contained within the package assembly. additional external input capacitance is required between this pin and exposed pad. output voltage ? output from the internal inductor. connect the output capacitor between vout 7 power this pin and exposed pad. 6 specifications 6.1 absolute maximum ratings (1) (2) (3) min max unit vin, ron to gnd ? 0.3 25 v en, fb, ss to gnd ? 0.3 7 v junction temperature 150 c peak reflow case temperature (30 sec) 245 c storage temperature, t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/ distributors for availability and specifications. (3) for soldering specifications, refer to the following document: snoa549 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) (2) 2000 v (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. manufacturing with less than 500-v hbm is possible with the necessary precautions. (2) the human body model is a 100-pf capacitor discharged through a 1.5-k ? resistor into each pin. test method is per jesd-22-114. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: lmz12002
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 6.3 recommended operating conditions (1) over operating free-air temperature range (unless otherwise noted) min max unit v in 4.5 20 v en 0 6.5 v operation junction temperature ? 40 125 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for specifications and test conditions, see the electrical characteristics. 6.4 thermal information lmz12002 thermal metric (1) ndw unit 7 pins r ja 4-layer jedec printed-circuit-board, 100 19.3 vias, no air flow junction-to-ambient thermal resistance (2) c/w 2-layer jedec printed-circuit-board, no 21.5 air flow r jc(top) junction-to-case (top) thermal resistance no air flow 1.9 c/w (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) r ja measured on a 1.705-in 3.0-in 4-layer board, with 1-oz. copper, thirty five thermal vias, no air flow, and 1-w power dissipation. refer to pcb layout diagrams. 6.5 electrical characteristics limits are for t j = 25 c unless otherwise specified. minimum and maximum limits are specified through test, design or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. unless otherwise stated the following conditions apply: v in = 12 v, v out = 1.8 v (1) . parameter test conditions min (2) typ (3) max (2) unit system parameters enable control 1.18 v en en threshold trip point v en rising v over the junction temperature 1.1 1.25 (t j ) range of -40 c to +125 c v en-hys en threshold hysteresis v en falling 90 mv soft-start 8 i ss ss source current v ss = 0 v a over the junction temperature 5 11 (t j ) range of -40 c to +125 c i ss-dis ss discharge current ? 200 a current limit 2.6 i cl current limit threshold dc average a over the junction temperature 2.3 3.65 (t j ) range of -40 c to +125 c on/off timer on timer minimum pulse t on-min 150 ns width t off off timer pulse width 260 ns (1) en 55022:2006, +a1:2007, fcc part 15 subpart b: 2007. see an-2024 and layout for information on device under test. (2) minimum and maximum limits are 100% production tested at 25 c. limits over the operating temperature range are specified through correlation using statistical quality control (sqc) methods. limits are used to calculate average outgoing quality level (aoql). (3) typical numbers are at 25 c and represent the most likely parametric norm. 4 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 electrical characteristics (continued) limits are for t j = 25 c unless otherwise specified. minimum and maximum limits are specified through test, design or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. unless otherwise stated the following conditions apply: v in = 12 v, v out = 1.8 v (1) . parameter test conditions min (2) typ (3) max (2) unit regulation and overvoltage comparator 0.795 v ss > + 0.8 v t j = -40 c to 125 c v over the junction temperature 0.775 0.815 i o = 2 a in-regulation feedback (t j ) range of -40 c to +125 c v fb voltage v ss > + 0.8 v t j = 25 c 0.784 0.8 0.816 i o = 10 ma feedback overvoltage v fb-ov 0.92 v protection threshold feedback input bias i fb 5 na current non-switching input i q v fb = 0.86 v 1 ma current shutdown quiescent i sd v en = 0 v 25 a current thermal characteristics t sd thermal shutdown rising 165 c thermal shutdown t sd-hyst falling 15 c hysteresis performance parameters v o output voltage ripple 8 mv pp v o / v in line regulation v in = 8 v to 20 v, i o = 2 a 0.01% v o / v in load regulation v in = 12 v 1.5 mv/a v in = 12 v, v o = 1.8 v, i o = 1 a 87% efficiency v in = 12 v, v o = 1.8 v, i o = 2 a 77% copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: lmz12002
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 6.6 typical characteristics unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 1. efficiency 4.5-v input at 25 c figure 2. dissipation 4.5-v input at 25 c figure 3. efficiency 5-v input at 25 c figure 4. dissipation 5-v input at 25 c figure 5. efficiency 6-v input at 25 c figure 6. dissipation 6-v input at 25 c 6 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.2 1.5 1.8 2.5 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 25c 1.8 1.2 1.5 2.5 output current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.2 1.5 1.8 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 output current (a) 25c 1.8 1.2 1.5 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.2 1.5 1.8 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 output current (a) 25c 1.8 1.2 1.5
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 typical characteristics (continued) unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 7. efficiency 8-v input at 25 c figure 8. dissipation 6-v input at 25 c figure 9. efficiency 12-v input at 25 c figure 10. dissipation 12-v input at 25 c figure 11. efficiency 20-v input at 25 c figure 12. dissipation 20-v input at 25 c copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: lmz12002 0 0.3 0.6 0.9 1.2 1.5 1.8 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.8 2.5 3.3 5.0 6.0 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 25c 1.8 2.5 3.3 5.0 6.0 output current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.2 1.5 1.8 2.5 3.3 5.0 6.0 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 25c 1.8 1.2 1.5 2.5 3.3 5.0 6.0 output current (a) 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.4 0.8 1.2 1.6 2 dissipation (w) 25c 1.2 1.5 1.8 2.5 3.3 5.0 output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 0 0.4 0.8 1.2 1.6 2 25c 1.8 1.2 1.5 2.5 3.3 5.0 output current (a)
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com typical characteristics (continued) unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 13. efficiency 4.5-v input at 85 c figure 14. dissipation 4.5-v input at 85 c figure 15. efficiency 5-v input at 85 c figure 16. dissipation 5-v input at 85 c figure 17. efficiency 6-v input at 85 c figure 18. dissipation 6-v input at 85 c 8 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 0 0.4 0.8 1.2 1.6 2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 dissipation (w) output current (a) 1.2 1.8 85c 2.5 1.5 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.5 1.2 1.8 2.5 85c 1.8 0 0.4 0.8 1.2 1.6 2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 dissipation (w) output current (a) 1.5 1.2 85c 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.5 1.2 1.8 85c 0 0.4 0.8 1.2 1.6 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 dissipation (w) output current (a) 1.5 1.2 1.8 85c 1.8 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.5 1.2 85c
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 typical characteristics (continued) unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 19. efficiency 8-v input at 85 c figure 20. dissipation 8-v input at 85 c figure 21. efficiency 12-v input at 85 c figure 22. dissipation 12-v input at 85 c figure 23. efficiency 20-v input at 85 c figure 24. dissipation 20-v input at 85 c copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: lmz12002 0 0.4 0.8 1.2 1.6 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 dissipation (w) output current (a) 1.8 3.3 5.0 2.5 85c 6.0 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.8 3.3 5.0 2.5 6.0 85c 0 0.4 0.8 1.2 1.6 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 dissipation (w) output current (a) 85c 1.2 1.5 1.8 2.5 3.3 5.0 6.0 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.5 1.2 1.8 2.5 3.3 5.0 6.0 85c 0 0.4 0.8 1.2 1.6 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 dissipation (w) output current (a) 1.8 3.3 5.0 2.5 1.5 1.2 85c 0 0.4 0.8 1.2 1.6 2 50 60 70 80 90 100 efficiency (%) output current (a) 1.8 3.3 5.0 2.5 1.5 1.2 85c
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com typical characteristics (continued) unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 25. line and load regulation at 25 c figure 26. line and load regulation at 85 c figure 27. output ripple 12 v in 3.3 v o 2 a 20 mv/div 1 figure 28. transient response 12 v in 3.3 v o 0.6-a to 2-a s/div step figure 29. current limit 1.8 v out at 25 c figure 30. current limit 3.3 v out at 25 c 10 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 input voltage (v) output current (a) onset short circuit 25c 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 input voltage (v) output current (a) short circuit onset 25c 20mv/div 20 mv/div 1.00 p s/div 50 mv/div 200 p s/div 0.5 a/div 0 0.4 0.8 1.2 1.6 2 output voltage (v) output current (a) 85c 4.5 5 6 12 8 20 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 1.825 0 0.4 0.8 1.2 1.6 2 output current (a) output voltage (v) 1.790 1.796 1.802 1.808 1.814 1.820 25c 20 4.5 12 5 8 6
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 typical characteristics (continued) unless otherwise specified, the following conditions apply: v in = 12 v; c in = 10- f x7r ceramic; c o = 100- f x7r ceramic; t a = 25 c for efficiency curves and waveforms. figure 32. thermal derating v out = 1.8 v figure 31. current limit 3.3 v out at 85 c copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: lmz12002 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 input voltage (v) output current (a) short circuit onset 85c 0 0.5 1 1.5 2 2.5 50 60 70 80 90 100 110 120 ambient temperature (c) output current (a) 4.5 v in 20 v in 12 v in ? ja = 19.6c/w v out = 1.8v
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 7 detailed description 7.1 overview the lmz12002 power module is an easy-to-use step-down dc-dc solution capable of driving up to 2-a load with exceptional power conversion efficiency, line and load regulation, and output accuracy. 7.2 functional block diagram 7.3 feature description 7.3.1 cot control circuit overview constant on-time control is based on a comparator and an on-time one-shot, with the output voltage feedback compared with an internal 0.8-v reference. if the feedback voltage is below the reference, the main mosfet is turned on for a fixed on-time determined by a programming resistor r on . r on is connected to v in such that on- time is reduced with increasing input supply voltage. following this on-time, the main mosfet remains off for a minimum of 260 ns. if the voltage on the feedback pin falls below the reference level again the on-time cycle is repeated. regulation is achieved in this manner. 7.3.2 output overvoltage comparator the voltage at fb is compared to a 0.92-v internal reference. if fb rises above 0.92 v the on-time is immediately terminated. this condition is known as overvoltage protection (ovp). it can occur if the input voltage is increased very suddenly or if the output load is decreased very suddenly. once ovp is activated, the top mosfet on-times will be inhibited until the condition clears. additionally, the synchronous mosfet will remain on until inductor current falls to zero. 7.3.3 current limit current limit detection is carried out during the off-time by monitoring the current in the synchronous mosfet. referring to the functional block diagram , when the top mosfet is turned off, the inductor current flows through the load, the pgnd pin and the internal synchronous mosfet. if this current exceeds 2.85 a (typical) the current limit comparator disables the start of the next on-time period. the next switching cycle will occur only if the fb input is less than 0.8 v and the inductor current has decreased below 2.85 a. inductor current is monitored during the period of time the synchronous mosfet is conducting. so long as inductor current exceeds 2.85 a, further on-time intervals for the top mosfet will not occur. switching frequency is lower during current limit due to the longer off-time. note current limit is dependent on both duty cycle and temperature as illustrated in the graphs in the typical characteristics section. 12 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 0.47 p f 10 p h co c in cvcc c bst fb en ss vin linear reg ron timer css r on r fbt r fbb c ff regulator ic v o internal passives vout gnd vin 1 2 3 4 5 6 7
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 feature description (continued) 7.3.4 thermal protection the junction temperature of the lmz12002 must not be allowed to exceed its maximum ratings. thermal protection is implemented by an internal thermal shutdown circuit which activates at 165 c (typical) causing the device to enter a low power standby state. in this state the main mosfet remains off causing v o to fall, and additionally the css capacitor is discharged to ground. thermal protection helps prevent catastrophic failures for accidental device overheating. when the junction temperature falls back below 145 c (typical hysteresis = 20 c) the ss pin is released, v o rises smoothly, and normal operation resumes. applications requiring maximum output current especially those at high input voltage may require application derating at elevated temperatures. 7.3.5 zero coil current detection the current of the lower (synchronous) mosfet is monitored by a zero coil current detection circuit which inhibits the synchronous mosfet when its current reaches zero until the next on-time. this circuit enables the dcm operating mode, which improves efficiency at light loads. 7.3.6 prebiased start-up the lmz12002 will properly start up into a prebiased output. this startup situation is common in multiple rail logic applications where current paths may exist between different power rails during the start-up sequence. the following scope capture shows proper behavior during this event. figure 33. prebiased start-up 7.4 device functional modes 7.4.1 discontinuous conduction and continuous conduction modes at light load the regulator will operate in discontinuous conduction mode (dcm). with load currents above the critical conduction point, it will operate in continuous conduction mode (ccm). when operating in dcm the switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to zero before the end of the off-time. note that during the period of time that inductor current is zero, all load current is supplied by the output capacitor. the next on-time period starts when the voltage on the at the fb pin falls below the internal reference. the switching frequency is lower in dcm and varies more with load current as compared to ccm. conversion efficiency in dcm is maintained because conduction and switching losses are reduced with the smaller load and lower switching frequency. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: lmz12002 enable 1 ms/div output current output voltage 2v pre-bias 3.3v output 2.0v/div 1.0a/div 1.0v/div
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lmz12002 is a step-down dc-to-dc power module. it is typically used to convert a higher dc voltage to a lower dc voltage with a maximum output current of 2 a. the following design procedure can be used to select components for the lmz12002. alternately, the webench software may be used to generate complete designs. when generating a design, the webench software utilizes iterative design procedure and accesses comprehensive databases of components. please go to www.ti.com for more details 8.2 typical application figure 34. evaluation board schematic diagram 8.2.1 design requirements for this example the following application parameters exist. ? v in range = up to 20 v ? v out = 0.8 v to 6 v ? i out = 2 a 8.2.2 detailed design procedure the lmz12002 is fully supported by webench and offers the following: component selection, electrical and thermal simulations as well as the build-it board for a reduction in design time. the following list of steps can be used to manually design the lmz12002 application. 1. select minimum operating v in with enable divider resistors 2. program v o with divider resistor selection 14 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 4 5 6 7 3 2 1 ep vout fb ron ss vin en gnd v in c in 2 10 p f enable 4.5v to 20v c ff 0.022 p f u1 c ss 0.022 p f r fbb 1.07k lmz12002tz-adj 1.8v o @ 2a c o 1 1 p f c o 2 100 p f r on 32.4k r ent 32.4k r enb 11.8k r fbt 1.37k c in 1 1 p f
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 typical application (continued) 3. program turnon time with soft-start capacitor selection 4. select c o 5. select c in 6. set operating frequency with r on 8.2.2.1 enable divider, r ent and r enb selection the enable input provides a precise 1.18-v band-gap rising threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as vin. the enable input also incorporates 90 mv (typical) of hysteresis resulting in a falling threshold of 1.09 v. the maximum recommended voltage into the en pin is 6.5 v. for applications where the midpoint of the enable divider exceeds 6.5 v, a small zener diode can be added to limit this voltage. the function of this resistive divider is to allow the designer to choose an input voltage below which the circuit will be disabled. this implements the feature of programmable under voltage lockout. this is often used in battery powered systems to prevent deep discharge of the system battery. it is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power- up. applying the enable divider to the main input rail is often done in the case of higher input voltage systems where a lower boundary of operation must be established. in the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the lmz12002 output rail. the two resistors must be chosen based on the following ratio: r ent / r enb = (v in uvlo / 1.18 v) ? 1 (1) the lmz12002 demonstration and evaluation boards use 11.8 k ? for r enb and 32.4 k ? for r ent resulting in a rising uvlo of 4.5 v. this divider presents 5.34 v to the en input when the divider input is raised to 20 v. the en pin is internally pulled up to vin and can be left floating for always-on operation. 8.2.2.2 output voltage selection output voltage is determined by a divider of two resistors connected between v o and ground. the midpoint of the divider is connected to the fb input. the voltage at fb is compared to a 0.8-v internal reference. in normal operation an on-time cycle is initiated when the voltage on the fb pin falls below 0.8 v. the main mosfet on- time cycle causes the output voltage to rise and the voltage at the fb to exceed 0.8 v. as long as the voltage at fb is above 0.8 v, on-time cycles will not occur. the regulated output voltage determined by the external divider resistors r fbt and r fbb is: v o = 0.8 v (1 + r fbt / r fbb ) (2) rearranging terms; the ratio of the feedback resistors for a desired output voltage is: r fbt / r fbb = (v o / 0.8 v) ? 1 (3) these resistors must be chosen from values in the range of 1.0 k to 10.0 k . for v o = 0.8 v the fb pin can be connected to the output directly so long as an output preload resistor remains that draws more than 20 a. converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present. a feed-forward capacitor is placed in parallel with r fbt to improve load step transient response. its value is usually determined experimentally by load stepping between dcm and ccm conduction modes and adjusting for best transient response and minimum output ripple. table 1 lists the values for r fbt , r fbb , c ff and r on . table 1. bill of materials ref des description case size manufacturer manufacturer p/n u1 simple switcher pfm-7 texas instruments lmz12002 tz c in1 1 f, 50 v, x7r 1206 taiyo yuden umk316b7105kl-t c in2 10 f, 50 v, x7r 1210 taiyo yuden umk325bj106mm-t c o1 1 f, 50 v, x7r 1206 taiyo yuden umk316b7105kl-t copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: lmz12002
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com typical application (continued) table 1. bill of materials (continued) ref des description case size manufacturer manufacturer p/n c o2 100 f, 6.3 v, x7r 1210 taiyo yuden jmk325bj10cr7mm-t r fbt 1.37 k ? 0603 vishay dale crcw06031k37fkea r fbb 1.07 k ? 0603 vishay dale crcw06031k07fkea r on 32.4 k ? 0603 vishay dale crcw060332k4fkea r ent 32.4 k ? 0603 vishay dale crcw060332k4fkea r enb 11.8 k ? 0603 vishay dale crcw060311k8fkea c ff 22 nf, 10%, x7r, 16 v 0603 tdk c1608x7r1h223k c ss 22 nf, 10%, x7r, 16 v 0603 tdk c1608x7r1h223k 8.2.2.3 soft-start capacitor selection programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. upon turn-on, after all uvlo conditions have been passed, an internal 8- a current source begins charging the external soft-start capacitor. the soft-start time duration to reach steady-state operation is given by the formula: t ss = v ref c ss / iss = 0.8 v c ss / 8 a (4) this equation can be rearranged as follows: c ss = t ss 8 a / 0.8 v (5) use of a 0.022- f capacitor results in 2.2-ms soft-start duration. this is recommended as a minimum value. as the soft-start input exceeds 0.8 v the output of the power stage will be in regulation. the soft-start capacitor continues charging until it reaches approximately 3.8 v on the ss pin. voltage levels between 0.8 v and 3.8 v have no effect on other circuit operation. note that the following conditions will reset the soft-start capacitor by discharging the ss input to ground with an internal 20- a current sink. ? the enable input being pulled low ? thermal shutdown condition ? overcurrent fault ? internal v cc uvlo (approx 4-v input to v in ) 8.2.2.4 c o selection none of the required c o output capacitance is contained within the module. at a minimum, the output capacitor must meet the worst case minimum ripple current rating of 0.5 i lr p-p , as calculated in equation 17 . beyond that, additional capacitance will reduce output ripple so long as the esr is low enough to permit it. a minimum value of 10 f is generally required. experimentation will be required if attempting to operate with a minimum value. ceramic capacitors or other low esr types are recommended. see an-2024 for more detail. equation 6 provides a good first pass approximation of c o for load transient requirements: c o i step v fb l v in / (4 v o (v in ? v o ) v out-tran ) (6) solving: c o 2 a 0.8 v 10 h 12 v / (4 3.3 v ( 12 v 3.3 v) 33 mv) 50 f (7) the lmz12002 demonstration and evaluation boards are populated with a 100 uf 6.3v x5r output capacitor. locations for extra output capacitors are provided. see an-2024 for locations. 16 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 8.2.2.5 c in selection the lmz12002 module contains an internal 0.47- f input ceramic capacitor. additional input capacitance is required external to the module to handle the input ripple current of the application. this input capacitance must be located in very close proximity to the module. input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. worst case input ripple current rating is dictated by equation 8 : i(c in(rms) ) ? 1 /2 i o (d / 1-d) where ? d ? v o / v in (8) as a point of reference, the worst case ripple current will occur when the module is presented with full load current and when v in = 2 v o . recommended minimum input capacitance is 10- f x7r ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. ti recommends to pay attention to the voltage and temperature deratings of the capacitor selected. note ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. if the system design requires a certain minimum value of input ripple voltage v in be maintained then equation 9 may be used. c in i o d (1 ? d) / f sw-ccm v in (9) if v in is 1% of v in for a 20-v input to 3.3-v output application this equals 200 mv and f sw = 400 khz. c in 2a 3.3 v / 20 v (1 ? 3.3 v / 20 v) / (400000 0.200 v) 3.4 f additional bulk capacitance with higher esr may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. 8.2.2.6 r on resistor selection many designs will begin with a desired switching frequency in mind. for that purpose equation 10 can be used. f sw(ccm) ? v o / (1.3 10 -10 r on ) (10) this can be rearranged as r on ? v o / (1.3 10 -10 f sw(ccm) (11) the selection of ron and f sw(ccm) must be confined by limitations in the on-time and off-time for the cot control circuit overview section. the on-time of the lmz12002 timer is determined by the resistor r on and the input voltage v in . it is calculated as follows: t on = (1.3 10 -10 r on ) / v in (12) the inverse relationship of t on and v in gives a nearly constant switching frequency as vin is varied. r on must be selected such that the on-time at maximum v in is greater than 150 ns. the on-timer has a limiter to ensure a minimum of 150 ns for t on . this limits the maximum operating frequency, which is governed by equation 13 : f sw(max) = v o / (v in(max) 150 ns) (13) this equation can be used to select r on if a certain operating frequency is desired so long as the minimum on- time of 150 ns is observed. the limit for r on can be calculated as follows: r on v in(max) 150 ns / (1.3 10 -10 ) (14) if r on calculated in equation 11 is less than the minimum value determined in equation 14 a lower frequency must be selected. alternatively, v in(max) can also be limited in order to keep the frequency unchanged. additionally, consider the minimum off-time of 260 ns limits the maximum duty ratio. larger r on (lower f sw ) must be selected in any application requiring large duty ratio. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: lmz12002
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 8.2.2.7 discontinuous conduction and continuous conduction modes selection operating frequency in dcm can be calculated as follows: f sw(dcm) ? v o (v in ? 1) 10 h 1.18 10 20 i o / (v in ? v o ) r on 2 (15) in ccm, current flows through the inductor through the entire switching cycle and never falls to zero during the off-time. the switching frequency remains relatively constant with load current and line voltage variations. the ccm operating frequency can be calculated using equation 7 above. following is a comparison pair of waveforms of the showing both ccm (upper) and dcm operating modes. v in = 12 v, v o = 3.3 v, i o = 2 a / 0.26 a 2 s/div figure 35. ccm and dcm operating modes the approximate formula for determining the dcm/ccm boundary is as follows: i dcb ? v o (v in ? v o ) / (2 10 h f sw(ccm) v in ) (16) figure 36 is a typical waveform showing the boundary condition. v in = 12 v, v o = 3.3 v, i o = 0.29 a 2 s/div figure 36. transition mode operation the inductor internal to the module is 10 h. this value was chosen as a good balance between low and high input voltage applications. the main parameter affected by the inductor is the amplitude of the inductor ripple current (i lr ). i lr can be calculated with: i lrp-p = v o (v in ? v o ) / (10 h f sw v in ) where ? v in is the maximum input voltage and f sw is determined from equation 10 . (17) if the output current i o is determined by assuming that i o = i l , the higher and lower peak of i lr can be determined. be aware that the lower peak of i lr must be positive if ccm operation is required. 18 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002 500 ma/div 2.00 p s/div 500 ma/div 2.00 p s/div
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 8.2.3 application curves v in = 12 v, v out = 5 v v in = 12 v, v out = 5 v figure 37. efficiency figure 38. thermal derating curve figure 39. radiated emissions (en 55022 class b) from evaluation board copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: lmz12002 0.0 10.0 30.0 40.0 50.0 70.0 0 frequency (mhz) radiated emissions (db p v/m) 20.0 60.0 80.0 200 400 600 800 1000 en 55022 class b limit 0 0.5 1 1.5 2 2.5 50 60 70 80 90 100 110 120 ambient temperature (c) output current (a) 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 output current (a) efficiency (%) 25c
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 9 power supply recommendations the lmz12002 device is designed to operate from an input voltage supply range between 4.5 v and 20 v. this input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. the resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the lmz12002 supply voltage that can cause a false uvlo fault triggering and system reset. if the input supply is more than a few inches from the lmz12002, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. the amount of bulk capacitance is not critical, but a 47- f or 100- f electrolytic capacitor is a typical choice. 10 layout 10.1 layout guidelines pcb layout is an important part of dc-dc converter design. poor board layout can disrupt the performance of a dc-dc converter and surrounding circuitry by contributing to emi, ground bounce and resistive voltage drop in the traces. these can send erroneous signals to the dc-dc converter resulting in poor regulation or instability. good layout can be implemented by following a few simple design rules. 1. minimize area of switched current loops. from an emi reduction standpoint, it is imperative to minimize the high di/dt current paths during pcb layout. the high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor c in1 is placed a distance away for the lmz12002. therefore physically place c in1 asa close as possible to the lmz12002 vin and gnd exposed pad. this will minimize the high di/dt area and reduce radiated emi. additionally, grounding for both the input and output capacitor must consist of a localized top side plane that connects to the gnd exposed pad (ep). 2. have a single point ground. the ground connections for the feedback, soft-start, and enable components must be routed to the gnd pin of the device. this prevents any switched or load currents from flowing in the analog ground traces. if not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. provide the single point ground connection from pin 4 to ep. 3. minimize trace length to the fb pin. both feedback resistors, r fbt and r fbb , and the feed forward capacitor c ff , must be located close to the fb pin. since the fb node is high impedance, maintain the copper area as small as possible. the trace are from r fbt , r fbb , and c ff must be routed away from the body of the lmz12002 to minimize noise. 4. make input and output bus connections as wide as possible. this reduces any voltage drops on the input or output of the converter and maximizes efficiency. to optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. doing so will correct for voltage drops and provide optimum output accuracy. 5. provide adequate device heat-sinking. use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom pcb layer. if the pcb has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. for best results use a 6 6 via array with a minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). ensure enough copper area is used for heat-sinking to keep the junction temperature below 125 c. 20 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 10.2 layout examples figure 40. critical current loops to minimize figure 41. pcb layout guide copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: lmz12002 ron en ss gnd fb vin 1 2 3 4 5 6 7 top view vin c out vout r ent r on c ss gnd thermal vias vout c in gnd r enb c ff r fbt r fbb gnd plane epad vin gnd v in v o c in1 c o1 loop 1 loop 2 lmz12002 vout high di/dt
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com layout examples (continued) figure 42. top view of evaluation pcb figure 43. bottom view of evaluation pcb 10.3 power dissipation and thermal considerations for the design case of v in = 12 v, v o = 3.3 v, i o = 2 a, t amb(max) = 85 c, and t junction = 125 c, the device must see a thermal resistance from case to ambient of: r ca < (t j-max ? t amb(max) ) / p ic-loss ? r jc (18) given the typical thermal resistance from junction to case to be 1.9 c/w. use the 85 c power dissipation curves in the typical characteristics section to estimate the p ic-loss for the application being designed. in this application it is 1.2 w r ca < (125 ? 85) / 1.2 w ? 1.9 = 31.4 (19) to reach r ca = 31.4, the pcb is required to dissipate heat effectively. with no airflow and no external heat, a good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is: 22 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 power dissipation and thermal considerations (continued) board area_cm 2 = 500 c cm 2 /w / r jc (20) as a result, approximately 15.9 square cm of 1-oz. copper on top and bottom layers is required for the pcb design. the pcb copper heat sink must be connected to the exposed pad. approximately thirty six, 8 mils thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. for an example of a high thermal performance pcb layout, refer to the demo board application note an-2024 ( snva422 ). 10.4 power module smt guidelines the recommendations below are for a standard module surface mount assembly ? land pattern ? follow the pcb land pattern with either soldermask defined or non-soldermask defined pads ? stencil aperture ? for the exposed die attach pad (dap), adjust the stencil for approximately 80% coverage of the pcb land pattern ? for all other i/o pads use a 1:1 ratio between the aperture and the land pattern recommendation ? solder paste ? use a standard sac alloy such as sac 305, type 3 or higher ? stencil thickness ? 0.125 to 0.15 mm ? reflow - refer to solder paste supplier recommendation and optimized per board size and density ? refer to design summary lmz1xxx and lmz2xxx power modules family ( snaa214 ) for reflow information. ? maximum number of reflows allowed is one figure 44. sample reflow profile table 2. sample reflow profile table max temp reached time above reached time above reached time above reached probe ( c) max temp 235 c 235 c 245 c 245 c 260 c 260 c 1 242.5 6.58 0.49 6.39 0.00 ? 0.00 ? 2 242.5 7.10 0.55 6.31 0.00 7.10 0.00 ? 3 241.0 7.09 0.42 6.44 0.00 ? 0.00 ? copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: lmz12002
lmz12002 snvs650h ? january 2010 ? revised august 2015 www.ti.com 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.1.2 development support for developmental support, see the following: webench tool, http://www.ti.com/webench 11.2 documentation support 11.2.1 related documentation for related documentation, see the following: ? an-2027 inverting application for the lmz14203 simple switcher power module , ( snva425 ) ? absolute maximum ratings for soldering , ( snoa549 ) ? an-2024 lmz1420x / lmz1200x evaluation board ( snva422 ) ? an-2085 lmz23605/03, lmz22005/03 evaluation board ( snva457 ) ? an-2054 evaluation board for lm10000 - powerwise avs system controller ( snva437 ) ? an-2020 thermal design by insight, not hindsight ( snva419 ) ? an-2026 effect of pcb design on thermal performance of simple switcher power modules ( snva424 ) ? design summary lmz1xxx and lmz2xxx power modules family ( snaa214 ) 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. webench, simple switcher are registered trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 24 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: lmz12002
lmz12002 www.ti.com snvs650h ? january 2010 ? revised august 2015 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: lmz12002
package option addendum www.ti.com 9-jul-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lmz12002tz-adj/nopb active to-pmod ndw 7 250 green (rohs & no sb/br) cu sn level-3-245c-168 hr -40 to 125 lmz12002 tz-adj lmz12002tze-adj/nopb active to-pmod ndw 7 45 green (rohs & no sb/br) cu sn level-3-245c-168 hr -40 to 125 lmz12002 tz-adj lmz12002tzx-adj/nopb active to-pmod ndw 7 500 green (rohs & no sb/br) cu sn level-3-245c-168 hr -40 to 125 lmz12002 tz-adj (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 9-jul-2015 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lmz12002tz-adj/nopb to- pmod ndw 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 q2 lmz12002tzx-adj/nop b to- pmod ndw 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 q2 package materials information www.ti.com 8-jul-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lmz12002tz-adj/nopb to-pmod ndw 7 250 367.0 367.0 45.0 lmz12002tzx-adj/nopb to-pmod ndw 7 500 367.0 367.0 45.0 package materials information www.ti.com 8-jul-2015 pack materials-page 2
mechanical da t a ndw0007a www .ti.com t z a 0 7 a ( r e v d ) t op side of p acka ge bo t t om side of p acka ge
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